1. Field of the Invention
The present invention relates to a semiconductor device and more particularly, to an improvement of reliability of electric contact between a semiconductor substrate and an interconnection layer and/or between interconnection layers.
2. Description of the Prior Art
FIG. 1 is a schematic cross sectional view showing a portion of a conventional semiconductor memory device in which a metal interconnection such as aluminum is electrically connected to an impurity diffusion region on the surface of a semiconductor substrate. Only a contact portion of a transfer gate transistor included in a memory cell of the semiconductor memory device is shown in FIG. 1. In FIG. 1, the transfer gate transistor comprises a semiconductor substrate 1 formed of a monocrystal silicon or the like, an impurity diffusion layer 2 formed as an active region by diffusing impurities such as arsenic into a predetermined region on the surface of the semiconductor substrate 1, a first metal interconnection layer 4 formed of polycrystalline silicon or the like and serving as a gate electrode of the transfer gate transistor, an interlayer insulating film 5 formed on the surface of the semiconductor substrate 1 and on the first metal interconnection layer 4, a second metal interconnection layer 3 electrically connected to the impurity diffusion layer 2 through a through-hole (a contact hole) 8 which is formed in a predetermined region of the interlayer insulating film 5 and reaches the surface of the impurity diffusion layer 2, and a surface protecting film 6 formed on the second interconnection layer 3. The interlayer insulating film 5 electrically isolates the first metal interconnection layer 4 from the second metal interconnection layer 3. More specifically, the semiconductor memory device shown in FIG. 1 has a two-layer interconnection structure comprising the second metal interconnection layer 3 electrically connected to the impurity diffusion layer 2 and the first metal interconnection layer 4 serving as a gate electrode of the transfer gate transistor.
In the conventional semiconductor device with a two-layer interconnection structure as described above, the contact hole 8 must be formed in the interlayer insulating film 5 to electrically connect the second metal interconnection layer 3 to the impurity diffusion layer 2 on the surface of the semiconductor substrate 1.
Due to the contact hole 8, a step occurs in the interlayer insulating film 5. Therefore, there is a problem in step coverage characteristics in a step portion of the second metal interconnection layer 3. The metal interconnection 3 on the side wall of the contact hole 8 is generally thinner than that on the interlayer insulating film 5. As a result, there were some problems, such as increase in interconnection resistance and contact resistance and deterioration in reliability caused by disconnection of interconnection.
Step coverage characteristics of a metal interconnection layer in a step portion of an insulating film is discussed in an article by T. Ito et al., entitled "ALUMINUM PLASMA-CVD FOR VLSI CIRCUIT INTERCONNECTIONS", 1982 Symposium on VLSI Technology Digest of Technical Papers, pp. 20-21. As described in the document, when an aluminum film is deposited by plasma CVD or sputtering in the step portion of a silicon dioxide (SiO.sub.2) film, the aluminum film formed on the side wall of the step is thinner than that formed on the planar portion.